7 Ways to Quickly Judge the Quality of Circuit Board Design (Part 3)

2-Decoupling capacitor

All chips need a power supply to function, but what happens if the power supply is a certain distance away from the chip that needs it? In these cases, the chip must be powered through the circuit board traces (although usually through the PCB power board on the inner layer). The location of the decoupling capacitor is very close to the power pin of the chip to filter out the negative effects of high-frequency noise on the chip. Generally, if a chip has multiple VDD pins, each such pin needs at least one decoupling capacitor, and sometimes more. The physical location of these decoupling capacitors should be very close to the pins to which they should be decoupled. If this does not happen, then its effect will be greatly reduced. If your PCB design does not place decoupling capacitors next to the power pins of most microchips, then your design has not been completed correctly. If you hire someone to design the PCB, but they did not handle the decoupling capacitors properly, then you should find a new designer.

3-The length of the PCB traces is balanced

In designs that require precise timing relationships between multiple signals, the length of the PCB traces must match. For example, this is critical when routing high-speed clock signals to multiple chips or data and address buses that run between a microprocessor and RAM memory. This ensures that all signals arrive at their destinations with the same delay, thus preserving the relationship between signal edges. This requires access to the schematic and to know which set of signal lines requires precise timing relationships. Then, trace the trace to see if some trace length equalization (called a delay line) has been achieved.

Note that vias in the signal path will cause additional delay. If these problems cannot be avoided, please check all traces that require precise timing relationships and make sure they have the same number of vias. Alternatively, you can use a delay line to compensate for the delay caused by the via.