Allegro Board to Board Reuse Tool Instruction

Program function: The module multiplexing enhancement function realizes three major functions. Function one: rapid reuse of modules on the board; function two: rapid reuse between boards according to the schematic page; function three: rapid reuse between boards according to the module. As a useful supplement to Allegro’s own module reuse function. The program supports ORCAD schematics and HDL schematics. AD schematic diagram and POWRERLOGIC principle can be converted into ORCAD schematic diagram for use.

1. Fast reuse of on-board modules

Modules in the board are quickly reused. Allegro’s own module reuse function has the following shortcomings.
1. Allegro’s own multiplexing function modules need to be matched one by one. When there are many small multiplexing modules on the board, it is still cumbersome to operate one by one. Use YEPEDA to automatically match all modules in a one-time program.
2. Allegro has its own reuse function. When the module layout needs to be changed, the operation is more troublesome and needs to be reused. With YEPEDA, all modules can be re-used and changed automatically by one-time program matching.
3. After module comparison and matching, a *.mah file will be generated, which can be used directly to quickly change the module layout. You can also use this file as a list file to quickly light up related devices.
Note: The multiplexed components of the module need to be on the same schematic page, otherwise the effect will not be good. If the module is complex and spans many schematic pages, and the scale is relatively large, it is recommended to use Allegro’s own multiplexing function.

2. Fast reuse between boards according to schematic diagram and page

For module multiplexing between boards, Allegro’s own multiplexing function has a relatively low success rate. Moreover, when multiplexing, the capacitors on the board are grabbed randomly, and the effect is not good. Using YEPEDA, you can correspond one-to-one with the device position on the schematic page, and automatically grab the layout. Can deal with layout reuse from multiple projects.

3. rapid reuse between boards according to modules

Realize the rapid reuse of the board layout of a small range of modules.

The match rate is currently set to 85%. This value can be set smaller according to the actual situation of the project. In order to improve the success rate of module reuse.
YEPEDA’s module reuse is realized based on the comparison of device positions in the schematic diagram. Therefore, it is necessary for the engineer to use this function when the device position of the schematic can be recognized by the naked eye. It doesn’t matter if the REF of the device is different, the position is the same.