How to Solve EMI Problems in Multilayer PCB Design (3)

10-Layer Board

Because the insulating isolation layer between the multi-layer boards is very thin, the impedance between the layers of the 10 or 12-layer circuit board is very low. As long as there is no problem with delamination and stacking, excellent signal integrity can be expected. It is more difficult to manufacture 12-layer boards with a thickness of 62 mil, and there are not many manufacturers that can process 12-layer boards.

Since there is always an insulating layer between the signal layer and the loop layer, it is not optimal to allocate the middle 6 layers to route the signal lines in the 10-layer board design. Also, it is important to have the signal layer adjacent to the loop layer, i.e. the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This design provides a good path for the signal current and its loop current. A proper routing strategy is to route the first layer along the X direction, the third layer along the Y direction, the fourth layer along the X direction, and so on. Intuitively looking at the line, layer 1 and layer 3 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are the last pair of layered combinations. When it is necessary to change the direction of the trace, the signal line on the first layer should be changed to the third layer through the “via hole”. In practice, it may not always be possible to do so, but as a design concept try to adhere to it.

Likewise, when the signal’s routing direction is changed, it should be via vias from layers 8 and 10 or from layer 4 to layer 7. Routing this way ensures the tightest coupling between the forward path and the return path of the signal. For example, if the signal is routed on layer 1 and the loop is routed on layer 2 and only on layer 2, even if the signal on layer 1 goes to layer 3 through a “via”, its loop is still on layer 2, thus maintaining low inductance, high capacitance, and good electromagnetic shielding performance.

If the actual wiring is not like this, what should we do? For example, the signal line on the 1st layer goes through the via to the 10th layer. At this time, the loop signal has to find the ground plane from the 9th layer, and the loop current needs to find the nearest ground via (such as ground pins for components such as resistors or capacitors). If you happen to have such a via nearby, you’re really lucky. If there are no such close vias available, the inductance will increase, the capacitance will decrease, and the EMI will definitely increase.

When the signal line must leave the current pair of wiring layers to other wiring layers through vias, ground vias should be placed near the vias, so that the loop signal can smoothly return to the appropriate grounding layer. For layer 4 and layer 7 layered combination, the signal loop will return from the power layer or the ground layer (ie layer 5 or layer 6), because the capacitive coupling between the power layer and the ground layer is good, and the signal is easy to transmit.

Design of Multiple Power Layers

If the two power layers of the same voltage source need to output a large current, the circuit board should be arranged into two groups of power layers and ground layers. In this case, insulating layers are placed between each pair of power and ground planes. This results in the two pairs of equal impedance power busbars that we expect to divide the current equally. If the stacking of power planes creates unequal impedances, the shunting will not be uniform, the transient voltage will be much larger, and EMI will increase dramatically.

If there are multiple supply voltages with different values ​​on the board, then multiple power planes are required accordingly, keeping in mind to create their own paired power and ground planes for the different power supplies. In both cases above, keep in mind the manufacturer’s requirements for a balanced structure when determining the placement of the mating power and ground planes on the board.

Summarize

Given that most engineers design boards as conventional printed circuit boards with a thickness of 62 mils and no blind or buried vias, this discussion of board layering and stacking is limited to that. For boards with too different thicknesses, the layering scheme recommended in this article may not be ideal. In addition, circuit boards with blind or buried vias are processed differently, and the layered approach in this paper is not applicable.

Thickness, via process and the number of layers in the pcb circuit board design are not the key to solving the problem. Excellent layered stacking is to ensure the bypass and decoupling of the power busbars and minimizes the transient voltage on the power or ground plane. And the key to shielding the electromagnetic fields of signals and power. Ideally, there should be an insulating isolation layer between the signal trace layer and its return ground layer, and the paired layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, a circuit board that can always meet the design requirements can be designed. Now that IC rise times are and will be shorter, the techniques discussed in this article are essential to solving EMI shielding problems.