Introduction To 4 Layer To 10 Layer Printed Circuit Board Design

4 layer PCB design

In general, for more complex high-speed circuits, it is better not to use a four-layer plate, because it has a number of unstable factors, both physical and electrical characteristics. If a four-layer board design is necessary, consider setting it as: power-signal-signal-ground. A better solution is to use both the outer layers and the inner layers to use power and signal lines. This scheme is the best stacking scheme for four-layer plate design, which has an excellent inhibition effect on EMI and is also very beneficial for reducing signal line impedance. However, this scheme has a small wiring space and is difficult for boards with a large wiring density.

6 layer PCB design

Many circuit boards today use six-layer PCB technology, such as the memory module PCB design, most of which use six-layer boards (high-capacity memory modules may use 10-layer boards). The most conventional six-layer lamination is arranged in this way: signal-ground signal-signal-power – signal. From the point of view of impedance control, this arrangement is reasonable, but because the power source is far from the ground plane, the radiation effect of small common mode EMI is not very good. If the copper-coated area is placed on the 3 and 4 layers, it will cause poor signal impedance control and strong differential mode EMI, etc.

There is another scheme to add a ground layer. The layout is signal-ground-signal-power-ground-signal. In this way, the environment needed for high-speed signal integrity design can be realized from both the point of view of impedance control and EMI reduction. The third layer is the signal routing layer, but the corresponding fourth layer is the power layer with a large area of copper coating, which may encounter some problems in the PCB manufacturing process. In the design, all the blank areas of the third layer can be coated with copper to achieve the effect of approximate balance structure.

A: The second and fifth layers are the power layer and ground copper. Due to the high impedance of power layer copper, it is very difficult to control common mode EMI radiation. However, from the point of view of signal impedance control, this method is quite correct. Because in this board layer design, Layer1 and Layer3 of signal routing layer, Layer4 and Layer6 constitute two relatively reasonable routing combinations.

B: The power layer and the ground are placed on the third and fourth layers respectively. This design solves the problem of the copper impedance of the power layer. Due to the poor electromagnetic shielding performance of the first layer and the sixth layer, the differential mode EMI is increased. This design can solve the differential EMI problem if the number of signal lines on the two outer layers is minimal and the line length is short (shorter than 1/20 of the wavelength of the highest harmonic wave of the signal). The non-element and non-wire area on the outer layer is filled with copper and grounded (1/20 wavelength interval), which is particularly good for the suppression of differential mode EMI.

C: From the point of view of signal quality, it is obvious that this arrangement of plates is the most reasonable. This structure is ideal for the high-frequency back-flow path of the signal. But this arrangement has a more prominent disadvantage, that is, the signal line layer is less. So such a system is suitable for high-performance requirements.

D: This enables the required environment for signal integrity design. The signal layer is adjacent to the ground layer, and the power layer is paired with the ground layer. Obviously, one drawback is that the layers are structurally unbalanced (unbalanced copper coating may cause warping of the PCB). The solution to the problem is to apply copper to all the blank areas of the third layer. If the copper density of the third layer is close to the power layer or the connecting layer after the copper application, the plate can be regarded as a structurally balanced circuit board loosely. Copper-clad areas must be powered or grounded.

8 layer PCB design

Most of the eight-layer plates in use today are designed to improve the signal quality of the six-layer plates. It can be seen from Table 3 that the eight-layer plate does not add the routing layer of signal compared with the six-layer plate, but adds two copper-clad layers, so the EMC performance of the system can be optimized.

10 Layer PCB design

The ten-layer PCB insulating medium layer is very thin, and the signal layer can be very close to the ground plane, which controls the impedance variation between layers very well. Generally, designers can easily complete the design of a high-quality high-speed circuit board as long as there is no serious laminated design error. If wiring is very complex and more wiring layers are needed, we can set the stacking layer as: signal-signal-ground signal-signal-signal-signal-power-signal-signal.

Of course, this situation is not the most ideal, we require the signal routing to be completed in a small number of layers, but the redundant layers are used to isolate other signal layers, so the more common stacking scheme is: signal-ground – signal-signal – signal-power – ground – signal-ground – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal – signal. As you can see, there are three ground layer and only one power layer (we only consider the single power layer case).

Although the impedance control effect of the power layer is the same as that of the ground plane layer, the voltage on the power layer is greatly disturbed, there are more high-order harmonics, and it is also strong to the external EMI, so it is best shielded by the ground plane, just like the signal routing layer. At the same time, if an additional power layer is used for isolation, the loop current will have to be converted from the ground plane to the power plane by decoupling the capacitance. In this way, too much voltage drop on the decoupling capacitor will produce unnecessary noise.