Latest PCB Cooling Technology (2)

Texas Instruments (TI) invented a PowerPAD method to mount IC die onto metal platters. This die pad will support the die during manufacturing and act as a good thermal path to dissipate heat away from the chip.

Matt Romig, TI’s analog packaging product manager, points out that TI’s PowerStack approach is the first 3D packaging technology that can stack high-side vertical MOSFETs. This technique integrates high-side and low-side MOSFETs held in place by copper clips and provides a thermally optimized design using an exposed pad at ground potential. The use of two copper clips to connect the input and output voltage pins allows for higher integration of flat quad no-lead (QFN) packaged power devices. Thermal management is more challenging. The need for higher frequency signal processing and shrinking package sizes have marginalized traditional cooling technologies. Kaver Azar, president and CEO of Advanced Thermal Solutions, recommends embedded thin-film thermoelectric devices with water-cooled microchannels.

Azar conceived a solution that minimizes the largest thermal resistance in the thermal path, the diffusion thermal resistance, by bonding a heat sink directly to the microprocessor die.

This method dissipates the heat accumulated on the small microprocessor die to the larger heat sink base, which then dissipates the heat to the surrounding environment. This built-in forced heat spreader integrates microchannels and minichannels in a silicon package. The water flow rate in the channel is approximately 0.5 to 1 liter/min.

Simulation results show that a 120×120mm heatsink chassis area can produce a thermal resistance of 0.055K/W on a 10×10mm die in a Ball Grid Array (BGA) package. Using a heat sink material with thermal conductivity equal to or greater than diamond can yield a thermal resistance of 0.030K/W.

Paul Magill, vice president of marketing and business development at Nextreme Thermal Solutions, also recommends thermoelectric cooling technology, claiming that cooling should start at the chip level. The company provides localized thermal management technology deep inside electronic components. The technology uses a tiny thin-film thermoelectric (eTEC) structure called a heat pump. This active heat dissipation material is embedded in flip-chip interconnects such as copper pillar solder bumps for use in electronic packaging.

Implementing localized cooling at the chip wafer, die, and package levels can yield important economic benefits. For example, in a data center with hundreds of advanced microprocessors, this approach is far more efficient than using more expensive and bulkier air conditioning systems to dissipate heat.

In some devices like LEDs, a combination of passive and active cooling techniques can improve device performance and lifetime. For example, using a fan in a heat sink can typically reduce thermal resistance to 0.5°C/W, which is a significant improvement over the typical 10°C/W achieved with passive cooling (heat sink) alone.

Re-emulation thermal control has been and continues to be one of the limiting factors in achieving higher IC performance. In these smaller and smaller ICs and their packages, space is increasingly at a premium, with little room left to help with cooling. This forces design engineers to consider the use of external cooling techniques as well as new cooling materials that are constantly improving.

Regardless, the basic premise still holds: Design engineers must pay more attention to thermal science to achieve optimal cooling solutions. The entire process should start with thermal analysis software long before the design goes into production.

This is the perfect time for simulation software tools to enter the market. Products such as Mentor Graphics’ Flotherm 3D V.9 software tool can help 3D IC designers determine heat generation and help them resolve thermal problems when they occur. This computational fluid dynamics (CFD) product provides maps of the bottleneck (Bn) and shortcut (Sc) fields. This allows engineers to know where heat flow congestion is occurring in the design and determine the reason.

According to Erich Bürgel, general manager of Mentor’s Mechanical Analysis Division, the innovative Bn field can indicate where the designed heat dissipation path is congested, as it always attempts to flow from the high junction temperature point to the ambient point. The Sc field highlights a possible way to create a new efficient heat flow path by adding a simple element such as a void pad or chassis protrusion.

Flotherm 3D V.9 supports importing XML models and geometric data to help the software integrate into the data flow. Flotherm also connects directly to Mentor’s Expedition PCB design platform. As a result, users can add, edit, or delete individual objects such as heat sinks, thermal vias, circuit board cutouts, and electromagnetic cans for more accurate thermal modeling.